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History

History

Step by step, toward smaller process nodes

Coressol's design capabilities, which began at 130nm, advanced to the 2nm process node in 2025.

Each year, Coressol continues to expand into more challenging process nodes, a wider range of Foundation IP, and future technology domains.

Advanced Technology 2020 - Present
  1. 2025

    • 1 Patent Registration (Korea)

    • Memory Compiler (2nm~5nm)

  2. 2024

    • 2 Patent Registrations (Korea)

    • Memory Compiler (2nm~5nm)

    • NVM IP (8nm~65nm)

  3. 2023

    • 1 Patent Registration

    • Library Test Chip : eFlash, eFuse, OTP

  4. 2022

    • DNA(Digital NVM Assistor)IP

    • MRAM-based PI

    • Memory Compiler (4nm~28nm)

  5. 2020

    • Standard Cell Library (4nm~5nm)

    • GPIO (65nm~180nm)

Expansion 2013 - 2019
  1. 2019

    • Awarded Samsung Foundry Best Design Partner Award

    • Memory Compiler (8nm~28nm)

    • NVM IP (28nm~90nm)

  2. 2017

    • Memory Compiler Test Chip : SRAM

  3. 2015

    • Memory Compiler (45nm~130nm) : SPSRAM, DPSRAM, RegFile

Foundation 2009 - 2012
  1. 2012

    • First Patent Registration

    • MRAM Development

  2. 2011

    • DDI Frame Memory Quality Certification

  3. 2010

    • Venture Company Certification

    • Securing Technical Capabilities

  4. 2009

    • Coressol Co., Ltd. Founded