HISTORY
CoresSol
HISTORY
CoresSol

HISTORY

2009


- Founded CoresSol Inc. 

- 1T RAM Joint Development (DDI Frame Memory Macro Test Chip)

- SRAM Macro (Single Port, Dual Port)


2010


- SRAM Macro (Block RAM for FPGA) 

2011


- 1T RAM Joint Development (DDI FRAME Memory Macro Test Chip Qual) 

- 1T RAM Macro (DDI Frame Memory(WVGA)) 

- SPSRAM Macro 

- Single Poly EEPROM Macro 

2012


- Patent Registration(1st) 

- SRAM Macro (Single Port 8Mbit Test Chip)

- MRAM Macro (DDI Frame Memory(Half QVGA))

2013


- Patent Registration(2nd)

- NOR-Flash Chip Design Experience 

- OTP, eFUSE Macro 

2014


- Patent Registration(3rd)

- NOR-Flash Chip Design Experience

- SRAM Macro : Area Reduction target 

2015


- Compiler : SPSRAM, 8T-DPSRAM, Register File

- SST eFLASH Sales Representative of Korea

- SRAM Memory Macro 

   - Single Port 4Mb Test Chip 

   - Single Port, Two Port @6T SRAM Cell

   - Dual Port Asynchronous @8T SRAM Cell 

2016


- Compiler (SPSRAM, Register File2, VROM, GRAM)

- SRAM Macro 

   - Single Port 8Mb Test Chip 

   - Dual Port @6T SRAM Cell 

2017


- Compiler (SPSRAM, Register File1, VROM)

- SRAM Macro (Single Port, Dual Port @6T SRAM Cell)

- Memory Compiler Test Chip 

2018


- Compiler 

   - SPSRAM, DPSRAM, Register File2, VROM 

   - OTP, eFLASH

- SRAM Macro (Single Port, Dual Port @6T SRAM Cell)

- Memory Compiler Test Chip 

2019


- Compiler 

   - SPSRAM, DPSRAM, Register File2, VROM

   - OTP, eFUSE, eFLASH, eMRAM

- SRAM Macro (Single Port, Dual Port @6T SRAM Cell)

- Standard Cell Library

- GPIO

2020


- Compiler 

   - SPSRAM, DPSRAM, Register File2, VROM

   - OTP, eFUSE, eFLASH, eMRAM

- SRAM Macro (Single Port, Dual Port @6T SRAM Cell)

- Standard Cell Library

- GPIO